Techfind proudly presents seminar report on Pipelined Heap Management

:: ABSTRACT ::


QualityofService(QoS) guarantees in networks are increasingly based on perflow queueing and sophisticated scheduling. Most advanced scheduling algorithms rely on a common computational primitive: priority queues. Large priority queues are built using calendar queue or heap data structures. To support advanced scheduling at OC192 (10 Gbps) rates and above, pipelined management of the priority queue is needed. We present a pipelined heap manager that we have designed as a core integratable into ASIC’s, in synthesizable Verilog form. We discuss how to use it in switches and routers, its advantages over calendar queues, and we present costperformance tradeoffs. Our design can be configured to any heap size. We have verified and synthesized our design and present cost and performance analysis

The speed of networks is increasing at a dramatic pace. Significant advances also occur in network architecture, and in particular in the provision of quality of service (QoS) guarantees. Switches and routers increasingly rely on specialized hardware to provide the desired high throughput and advanced QoS. Such supporting hardware becomes feasible
and economical owing to the advances in semiconductor technology. To be able to provide toplevel QoS guarantees, network switches and routers increasingly rely on perflow queueing and advanced scheduling [14]. The topic of this paper is hardware support for advanced scheduling.

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